1. Field of the Invention
The present invention relates to binary number conversion and more particularly to providing a unique substitute binary number, from a limited range of numbers, for each of selectable ones of input binary numbers having a relatively large range.
2. Related Patent Applications
The following applications, including this application, assigned to the assignee of this application, have been filed on even date herewith:
1. U.S. Pat. No. 4,422,144 entitled "Microinstruction Substitution Mechanism In A Control Store Element", invented by L. H. Johnson et al.
2. Ser. No. 269,147 entitled "An Improved Binary Number Substitution Mechanism" invented by F. T. Blount; and
3. Ser. No. 269,148 now abandoned entitled "Microcode Control of Microinstruction Substitution In A Control Store Mechanism" invented by E. A. Nadarzynski et al.
3. Patents Incorporated by Reference
The following U.S. patents, all assigned to the assignee of the present invention, disclose various elements of a control store mechanism utilizing the present invention, and are herewith incorporated by reference:
1. U.S. Pat. No. 3,800,293 issued Mar. 26, 1974, entitled "Microprogram Control Sub-System" by T. A. Enger et al.
2. U.S. Pat. No. 3,958,227 issued May 18, 1976, entitled "Control Store System With Flexible Control Word Selection" by C. W. Evans.
3. U.S. Pat. No. 3,976,865 issued Aug. 24, 1976, entitled "Error Detector For An Associative Directory Or Translator" by T. A. Enger.
4. U.S. Pat. No. 4,008,460 issued Feb. 15, 1977, entitled "Circuit For Implementing A Modified LRU Replacement Algorithm For A Cache" by L. R. Bryant et al.
4. Prior Art
In stored program data processing systems, two techniques for control of the data processing system are normally implemented. One involves the design of hardwired sequencers, and the other involves the design of a control store element (CSE) comprised of storage devices for storing sequences of micro-instructions making up microprograms. In either case, machine instructions transferred from main storage to the central processing unit will be interpreted to determine the coding of an operation code portion of the instruction to determine the function to be performed such as Add, Subtract, Multiply, etc. When a CSE is utilized, the operation code will normally be utilized to address a storage device to access the first micro-instruction of a microprogram effective to execute the function called for by the operation code.
An excellent discussion of the various forms that a CSE can take is found in an article entitled "Microprogramming: Perspective and Status" by A. J. Agrawala and T. G. Rauscher, IEEE Transactions On Computers, Volume C-23, No. 8, August 1974, Page 817. One form of CSE includes at least two types of storage devices utilized for storing sequences of microinstructions making up microprograms. One type of storage device is a read-only store (ROS), and the other is a writeable control store (WCS). The ROS will be comprised of binary bit patterns which make up addressable microinstructions and which, during operation of the data processing system, will never be altered. In some data processing systems, the ROS may in fact be a permanently configured storage device created during manufacture of the data processing system. Another form of ROS would be a volatile storage device in which information can be stored, as necessary, but once initialized or loaded with microinstructions, will thereafter not be modified during processing functions. On the other hand, a WCS will be an addressable storage device of the read-write type wherein microinstructions can be dynamically stored into the storage device and thereafter read or accessed for use, and would be dynamically changed as conditions required during data processing. Examples of this type of CSE configuration are represented by U.S. Pat. Nos. 3,478,322 and 3,735,363.
Contempory data processing systems which include a CSE, also include a central processing unit and a main storage device for the storage of data and programs to be executed by the system. Also included is a processor controller, or console, which provides basic control for the entire system. It is the function of the processor controller, when power is turned on to the data processing system, to load necessary information into the data processing system.
The main storage device has a portion reserved for a number of system control data blocks, including all of the microprograms required to operate the system. This reserved portion of main storage is not addressable by program instructions executed by the system, but is primarily addressable by the central processing unit under control of microinstructions. To initialize the data processor, the processor controller will transfer all of the microcode, and other control information required by the system, to the reserved portion of main storage. By utilizing special data paths, the processor controller has the ability to store prespecified information into various registers, triggers, or storage arrays within the central processing unit, including the ROS of the CSE, if the ROS is a read-write type of storage device. If the ROS is a permanent storage device this would not be required. When a WCS is provided, this may be initialized by the processor controller or, as a minimum, the processor controller will store all of the microcode that may be utilized in the WCS into the main storage device.
The use of ROS in a CSE is normally for frequently used microcode. Its construction is such that it is very dense and high speed, but is relatively expensive when compared with a WCS. As the design of a data processing system progresses, a point will be reached where all of the microprograms have been written for the frequent processing functions required. A ROS storage device will be manufactured with the permanent bit patterns required to provide the necessary sequence of microinstructions. It is frequently discovered during the data processing system design, or after design has been completed, that certain of the previously created microinstructions in the ROS are erroneous. Another error situation that can occur with the ROS, even after the entire data processing system has been designed and erroneous microinstructions corrected, is that the hardware mechanism of the ROS may develop a failure which is permanent. Also, the creation of microcode that is permanently stored in a ROS is initially dictated by known features, functions and instructions to be executed when the data processing system is designed. New features, changing functions, or newly defined program instructions requiring modifications to the bit patterns of a ROS would require a long and expensive procedure, and systems already in use could not be modified easily.
The above-cited Related Application 1 describes a microinstruction substitution mechanism where substitute microinstructions are transferred from main storage to a WCS from a main storage address which is a function of the address of a faulty microinstruction read from ROS.